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Event Details

About

What is eInfochips?

eInfochips is a Global Product Design Services and Solutions company providing end-to-end Product Engineering and Semiconductor Services since 1994 to various key industry verticals, including Consumer Electronics, Aerospace and Defence, Healthcare, Semiconductor, Machine Vision and Image Processing, Security Surveillance, Video and Automotive Industry by bringing innovation in each stage of product development.

eInfochips offers a broad portfolio of services comprising New Product Development, Product Sustenance and Maintenance , Product QA & Independent Testing, , Hardware & Software Design, Product Re-engineering, Complete Product Lifecycle Management, compliance and certification, Application Development and Integration, Enterprise IT consulting and implementation, ASIC/ FPGA Design, RTL to GDSII (Design, Verification, Physical Design), FPGA Design & Prototyping and IP Cores Development and Integration etc.

Information regarding various domains

Domain

Required Branch

C / OOP

Digital

Logic

Design

CMOS

Micro

Controller

DS,

OS

 

Basic Electronics

ASIC DV and Physical Design

EC, CE

 

Device Driver i.e. Embedded Software Developer

EC,CE,IT

 

 

 

Hardware Board Designing

 

EC

 

 

 

Software Development

CE,IT,MCA,MSC-IT

 

 

 

 

QA and Testing

CE,IT,MCA,MSC-IT

 

 

 

 

 

 

Roles and Job Responsibilities after entering into the domain

·         ASIC DV and Physical Design Engineer: ASIC Stream has three internal job profiles, which can be exampled as below. On successful selection of engineer, candidate will be allocated to one of the stream based on his/her written exam score and personal interview feedback. Responsibility for each stream is exampled below.

o   Verification Engineer: Responsible for defining and developing the verification environment, developing test plans and generation of high quality test cases for verification of different blocks in the design and to achieve high functionality and code coverage to make sure the correctness of RTL design.

o   Physical Design Engineer: Work closely with front end design engineers to translate RTL-to-GDSII. Responsible for all aspects of physical design and implementation. Participate in the efforts of establishing physical design methodologies and flow automation.

o   FPGA Design Engineer: FPGA Development from simple glue logic to extensive System on a Chip (SoC) designs. FPGA design services include RTL coding, FPGA Design Partitioning, FPGA verification, Synthesis, Floor planning, Place & Route, FPGA implementation, FPGA Board Bring-up.

Note: EC Branch student will be considered for ASIC Verification profile only.

·         Device Driver Engineer: Responsible for writing the kernel program, will be working on Embedded- ARM platform, writing up of shell scripts

·         Hardware Board Designer:  Debugging / Testing of hardware board at initial level and then will be responsible for designing of hardware board  to support features that are included as part of new product definitions.

·         Software Developer: Develop, create, and modify general computer applications software or specialized utility programs. Analyze user needs and develop software solutions. Design software or customize software for client use with the aim of optimizing operational efficiency.

 

·         QA and Testing Engineer: Responsible for creating an end-to-end test plan; executing the plan and managing all activities in the plan to ensure that all the objectives are met and that the solution works as expected.


Training Norms

              

·       Candidates need to submit a PDC before joining eiTRA training; it’s the amount which would be secured as fees of eiTRA training program.

·       For ASIC: 75000+Service Tax, PES: 50,000+Service Tax & for QA: 30,000+12.36%Service Tax.

·       You need to pay only half of the amount after joining E-infochips which may directly deduct from your E-Infochips salary account in installments or as required.

·       Duration of the training would be 4 to 6 months approx.

·       The amount will not be deducted if candidates get rejection from e-Infochips.

·       PDC would be submitted to eiTRA account, incase candidate does not join e-Infochips even after selection so fees would be treated as eiTRA training fees.   

·       It will not applicable to students who are selected directly and it will applicable to those only who needs to go through traning.




Contact

Krunal Patel
TPO-GPERI

www.einfochips.com

Schedule

October 15, 2015 — 9:00 am to
October 16, 2015 — 6:00 pm

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Venue

GPERI Campus
Ahmedabad-Mehsana Highway
Near Toll Booth
Gujarat, Gujarat
India

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